Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Xilinx SuperSpeed DWC3 USB SoC controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible:	Should contain "xlnx,zynqmp-dwc3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - clocks:	A list of phandles for the clocks listed in clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - clock-names:	Should contain the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)   "bus_clk"	 Master/Core clock, have to be >= 125 MHz for SS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 		 operation and >= 60MHz for HS operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   "ref_clk"	 Clock source to core during PHY power down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Required child node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) A child node must exist to represent the core DWC3 IP block. The name of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) the node is not important. The content of the node is defined in dwc3.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Example device node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		usb@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 			#address-cells = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 			#size-cells = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 			compatible = "xlnx,zynqmp-dwc3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 			clock-names = "bus_clk" "ref_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 			clocks = <&clk125>, <&clk125>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 			ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 			dwc3@fe200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 				compatible = "snps,dwc3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 				reg = <0x0 0xfe200000 0x40000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 				interrupts = <0x0 0x41 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 				dr_mode = "host";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		};