^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * USB2 ChipIdea USB controller for ci13xxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: should be one of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) "fsl,imx23-usb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) "fsl,imx27-usb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) "fsl,imx28-usb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) "fsl,imx6q-usb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) "fsl,imx6sl-usb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) "fsl,imx6sx-usb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) "fsl,imx6ul-usb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "fsl,imx7d-usb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "fsl,imx7ulp-usb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "lsi,zevio-usb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "qcom,ci-hdrc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) "chipidea,usb2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "xlnx,zynq-usb-2.20a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) "nvidia,tegra20-udc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) "nvidia,tegra30-udc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) "nvidia,tegra114-udc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) "nvidia,tegra124-udc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - reg: base address and length of the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - interrupts: interrupt for the USB controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Recommended properies:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - phy_type: the type of the phy connected to the core. Should be one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) property the PORTSC register won't be touched.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Deprecated properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - usb-phy: phandle for the PHY device. Use "phys" instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - fsl,usbphy: phandle of usb phy that connects to the port. Use "phys" instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - clocks: reference to the USB clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - phys: reference to the USB PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - phy-names: should be "usb-phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - vbus-supply: reference to the VBUS regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - maximum-speed: limit the maximum connection speed to "full-speed".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - itc-setting: interrupt threshold control register control, the setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) should be aligned with ITC bits at register USBCMD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - ahb-burst-config: it is vendor dependent, the required value should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) aligned with AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) property is used to change AHB burst configuration, check the chipidea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) spec for meaning of each value. If this property is not existed, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) will use the reset value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - tx-burst-size-dword: it is vendor dependent, the tx burst size in dword
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) (4 bytes), This register represents the maximum length of a the burst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) in 32-bit words while moving data from system memory to the USB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) bus, the value of this property will only take effect if property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "ahb-burst-config" is set to 0, if this property is missing the reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) default of the hardware implementation will be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - rx-burst-size-dword: it is vendor dependent, the rx burst size in dword
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) (4 bytes), This register represents the maximum length of a the burst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) in 32-bit words while moving data from the USB bus to system memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) the value of this property will only take effect if property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "ahb-burst-config" is set to 0, if this property is missing the reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) default of the hardware implementation will be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) - extcon: phandles to external connector devices. First phandle should point to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) external connector, which provide "USB" cable events, the second should point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) to external connector device, which provide "USB-HOST" cable events. If one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) of the external connector devices is not required, empty <0> phandle should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) be specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) - phy-clkgate-delay-us: the delay time (us) between putting the PHY into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) low power mode and gating the PHY clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) - non-zero-ttctrl-ttha: after setting this property, the value of register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ttctrl.ttha will be 0x7f; if not, the value will be 0x0, this is the default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) value. It needs to be very carefully for setting this property, it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) recommended that consult with your IC engineer before setting this value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) On the most of chipidea platforms, the "usage_tt" flag at RTL is 0, so this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) property only affects siTD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) If this property is not set, the max packet size is 1023 bytes, and if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) the total of packet size for pervious transactions are more than 256 bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) it can't accept any transactions within this frame. The use case is single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) transaction, but higher frame rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) If this property is set, the max packet size is 188 bytes, it can handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) more transactions than above case, it can accept transactions until it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) considers the left room size within frame is less than 188 bytes, software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) needs to make sure it does not send more than 90%
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) maximum_periodic_data_per_frame. The use case is multiple transactions, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) less frame rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) - mux-controls: The mux control for toggling host/device output of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) controller. It's expected that a mux state of 0 indicates device mode and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mux state of 1 indicates host mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) - mux-control-names: Shall be "usb_switch" if mux-controls is specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) - pinctrl-names: Names for optional pin modes in "default", "host", "device".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) In case of HSIC-mode, "idle" and "active" pin modes are mandatory. In this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case, the "idle" state needs to pull down the data and strobe pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) and the "active" state needs to pull up the strobe pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) - pinctrl-n: alternate pin modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) i.mx specific properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) - fsl,usbmisc: phandler of non-core register device, with one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) argument that indicate usb controller index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) - disable-over-current: disable over current detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) - over-current-active-low: over current signal polarity is active low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) - over-current-active-high: over current signal polarity is active high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) It's recommended to specify the over current polarity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) - power-active-high: power signal polarity is active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) - external-vbus-divider: enables off-chip resistor divider for Vbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) - samsung,picophy-pre-emp-curr-control: HS Transmitter Pre-Emphasis Current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) Control. This signal controls the amount of current sourced to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) USB_OTG*_DP and USB_OTG*_DN pins after a J-to-K or K-to-J transition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) The range is from 0x0 to 0x3, the default value is 0x1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) Details can refer to TXPREEMPAMPTUNE0 bits of USBNC_n_PHY_CFG1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) - samsung,picophy-dc-vol-level-adjust: HS DC Voltage Level Adjustment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) Adjust the high-speed transmitter DC level voltage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) The range is from 0x0 to 0xf, the default value is 0x3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) usb@f7ed0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) compatible = "chipidea,usb2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) reg = <0xf7ed0000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clocks = <&chip CLKID_USB0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) phys = <&usb_phy0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) phy-names = "usb-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) vbus-supply = <®_usb0_vbus>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) itc-setting = <0x4>; /* 4 micro-frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Incremental burst of unspecified length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ahb-burst-config = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) tx-burst-size-dword = <0x10>; /* 64 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) rx-burst-size-dword = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) extcon = <0>, <&usb_id>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) phy-clkgate-delay-us = <400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mux-controls = <&usb_switch>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mux-control-names = "usb_switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) Example for HSIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) usb@2184400 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) reg = <0x02184400 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) clocks = <&clks IMX6QDL_CLK_USBOH3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) fsl,usbphy = <&usbphynop1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) fsl,usbmisc = <&usbmisc 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) phy_type = "hsic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dr_mode = "host";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ahb-burst-config = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) tx-burst-size-dword = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) rx-burst-size-dword = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pinctrl-names = "idle", "active";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pinctrl-0 = <&pinctrl_usbh2_idle>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) pinctrl-1 = <&pinctrl_usbh2_active>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) usbnet: smsc@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) compatible = "usb424,9730";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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