^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Universal Flash Storage (UFS) Host Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) UFSHC nodes are defined to describe on-chip UFS host controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Each UFS controller instance should have its own node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) For Qualcomm SoCs must contain, as below, an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) SoC-specific compatible along with "qcom,ufshc" and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) the appropriate jedec string:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - interrupts : <interrupt mapping for UFS host controller IRQ>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - reg : <registers mapping>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - phys : phandle to UFS PHY node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - phy-names : the string "ufsphy" when is found in a node, along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) with "phys" attribute, provides phandle to UFS PHY node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - vdd-hba-supply : phandle to UFS host controller supply regulator node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - vcc-supply : phandle to VCC supply regulator node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - vccq-supply : phandle to VCCQ supply regulator node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - vccq2-supply : phandle to VCCQ2 supply regulator node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) or 2.7-3.6V. This boolean property when set, specifies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) to use low voltage range of 1.7-1.95V. Note for external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) UFS cards this property is invalid and valid VCC range is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) always 2.7-3.6V.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - vcc-max-microamp : specifies max. load that can be drawn from vcc supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - vccq-max-microamp : specifies max. load that can be drawn from vccq supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - clocks : List of phandle and clock specifier pairs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - clock-names : List of clock input name strings sorted in the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) order as the clocks property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "ref_clk" indicates reference clock frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) UFS host supplies reference clock to UFS device and UFS device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) specification allows host to provide one of the 4 frequencies (19.2 MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) parsed and used to update the reference clock setting in device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Defaults to 26 MHz(as per specification) if not specified by host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - freq-table-hz : Array of <min max> operating frequencies stored in the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) order as the clocks property. If this property is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) defined or a value in the array is "0" then it is assumed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) that the frequency is set by the parent clock or a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) fixed rate clock source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) -lanes-per-direction : number of lanes available per direction - either 1 or 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) Note that it is assume same number of lanes is used both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) directions at once. If not specified, default is 2 lanes per direction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - #reset-cells : Must be <1> for Qualcomm UFS controllers that expose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PHY reset from the UFS controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) - resets : reset node register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) - reset-names : describe reset node register, the "rst" corresponds to reset the whole UFS IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) - reset-gpios : A phandle and gpio specifier denoting the GPIO connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) to the RESET pin of the UFS memory device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) Note: If above properties are not defined it can be assumed that the supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) regulators or clocks are always on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ufshc@fc598000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) compatible = "jedec,ufs-1.1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) reg = <0xfc598000 0x800>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) interrupts = <0 28 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) vdd-hba-supply = <&xxx_reg0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) vcc-supply = <&xxx_reg1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) vcc-supply-1p8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) vccq-supply = <&xxx_reg2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) vccq2-supply = <&xxx_reg3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) vcc-max-microamp = 500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) vccq-max-microamp = 200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) vccq2-max-microamp = 200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) clocks = <&core 0>, <&ref 0>, <&phy 0>, <&iface 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) clock-names = "core_clk", "ref_clk", "phy_clk", "iface_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) resets = <&reset 0 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) reset-names = "rst";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) phys = <&ufsphy1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) phy-names = "ufsphy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #reset-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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