Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Each UFS PHY node should have its own node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) To bind UFS PHY with UFS host controller, the controller node should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) contain a phandle reference to UFS PHY node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - compatible        : compatible list, contains one of the following -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 			"qcom,ufs-phy-qmp-20nm" for 20nm ufs phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 			"qcom,ufs-phy-qmp-14nm" for legacy 14nm ufs phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 			"qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 			 present on MSM8996 chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - reg               : should contain PHY register address space (mandatory),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - reg-names         : indicates various resources passed to driver (via reg proptery) by name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)                       Required "reg-names" is "phy_mem".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - #phy-cells        : This property shall be set to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - vdda-phy-supply   : phandle to main PHY supply for analog domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - vdda-pll-supply   : phandle to PHY PLL and Power-Gen block power supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - clocks	    : List of phandle and clock specifier pairs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - clock-names       : List of clock input name strings sorted in the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		      order as the clocks property. "ref_clk_src", "ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		      "tx_iface_clk" & "rx_iface_clk" are mandatory but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		      "ref_clk_parent" is optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - vdda-phy-max-microamp : specifies max. load that can be drawn from phy supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - vddp-ref-clk-supply   : phandle to UFS device ref_clk pad power supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - resets : specifies the PHY reset in the UFS controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	ufsphy1: ufsphy@fc597000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		compatible = "qcom,ufs-phy-qmp-20nm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		reg = <0xfc597000 0x800>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		reg-names = "phy_mem";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		#phy-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		vdda-phy-supply = <&pma8084_l4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		vdda-pll-supply = <&pma8084_l12>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		vdda-phy-max-microamp = <50000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		vdda-pll-max-microamp = <1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		clock-names = "ref_clk_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			"ref_clk_parent",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			"ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			"tx_iface_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			"rx_iface_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		clocks = <&clock_rpm clk_ln_bb_clk>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 			<&clock_gcc clk_pcie_1_phy_ldo >,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			<&clock_gcc clk_ufs_phy_ldo>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			<&clock_gcc clk_gcc_ufs_tx_cfg_clk>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			<&clock_gcc clk_gcc_ufs_rx_cfg_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		resets = <&ufshc 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	ufshc: ufshc@fc598000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		#reset-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		phys = <&ufsphy1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		phy-names = "ufsphy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	};