Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Mediatek Universal Flash Storage (UFS) Host Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) UFS nodes are defined to describe on-chip UFS hardware macro.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Each UFS Host Controller should have its own node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) To bind UFS PHY with UFS host controller, the controller node should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) contain a phandle reference to UFS M-PHY node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Required properties for UFS nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - compatible         : Compatible list, contains the following controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)                        "mediatek,mt8183-ufshci" for MediaTek UFS host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)                        present on MT8183 chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)                        "mediatek,mt8192-ufshci" for MediaTek UFS host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)                        present on MT8192 chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - reg                : Address and length of the UFS register set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - phys               : phandle to m-phy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clocks             : List of phandle and clock specifier pairs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - clock-names        : List of clock input name strings sorted in the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)                        order as the clocks property. "ufs" is mandatory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)                        "ufs": ufshci core control clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - freq-table-hz      : Array of <min max> operating frequencies stored in the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)                        order as the clocks property. If this property is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)                        defined or a value in the array is "0" then it is assumed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)                        that the frequency is set by the parent clock or a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)                        fixed rate clock source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - vcc-supply         : phandle to VCC supply regulator node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	ufsphy: phy@11fa0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	ufshci@11270000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		compatible = "mediatek,mt8183-ufshci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		reg = <0 0x11270000 0 0x2300>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		phys = <&ufsphy>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		clocks = <&infracfg_ao INFRACFG_AO_UFS_CG>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		clock-names = "ufs";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		freq-table-hz = <0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		vcc-supply = <&mt_pmic_vemc_ldo_reg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	};