Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Hisilicon Universal Flash Storage (UFS) Host Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) UFS nodes are defined to describe on-chip UFS hardware macro.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Each UFS Host Controller should have its own node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - compatible        : compatible list, contains one of the following -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 					"hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 					host controller present on Hi3660 chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 					"hisilicon,hi3670-ufs", "jedec,ufs-2.1" for hisi ufs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 					host controller present on Hi3670 chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - reg               : should contain UFS register address space & UFS SYS CTRL register address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - interrupts        : interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - clocks	        : List of phandle and clock specifier pairs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - clock-names       : List of clock input name strings sorted in the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 					order as the clocks property. "ref_clk", "phy_clk" is optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - freq-table-hz     : Array of <min max> operating frequencies stored in the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)                       order as the clocks property. If this property is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)                       defined or a value in the array is "0" then it is assumed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)                       that the frequency is set by the parent clock or a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)                       fixed rate clock source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - resets            : describe reset node register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - reset-names       : reset node register, the "rst" corresponds to reset the whole UFS IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	ufs: ufs@ff3b0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		/* 0: HCI standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		/* 1: UFS SYS CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		reg = <0x0 0xff3b0000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			<0x0 0xff3b1000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		interrupt-parent = <&gic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		clock-names = "ref_clk", "phy_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		freq-table-hz = <0 0>, <0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		/* offset: 0x84; bit: 12  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		resets = <&crg_rst 0x84 12>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		reset-names = "rst";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	};