Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Mediatek Thermal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This describes the device tree binding for the Mediatek thermal controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) which measures the on-SoC temperatures. This device does not have its own ADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) instead it directly controls the AUXADC via AHB bus accesses. For this reason
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) this device needs phandles to the AUXADC. Also it controls a mux in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) is also needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   - "mediatek,mt8173-thermal" : For MT8173 family of SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   - "mediatek,mt2701-thermal" : For MT2701 family of SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   - "mediatek,mt2712-thermal" : For MT2712 family of SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   - "mediatek,mt7622-thermal" : For MT7622 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   - "mediatek,mt8183-thermal" : For MT8183 family of SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - reg: Address range of the thermal controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - interrupts: IRQ for the thermal controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - clocks, clock-names: Clocks needed for the thermal controller. required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)                        clocks are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		       "therm":	 Main clock needed for register access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		       "auxadc": The AUXADC clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - resets: Reference to the reset controller controlling the thermal controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - mediatek,apmixedsys: A phandle to the APMIXEDSYS controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - #thermal-sensor-cells : Should be 0. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)                unspecified default values shall be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - nvmem-cell-names: Should be "calibration-data"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	thermal: thermal@1100b000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		#thermal-sensor-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		compatible = "mediatek,mt8173-thermal";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		reg = <0 0x1100b000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		clock-names = "therm", "auxadc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		reset-names = "therm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		mediatek,auxadc = <&auxadc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		mediatek,apmixedsys = <&apmixedsys>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		nvmem-cells = <&thermal_calibration_data>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		nvmem-cell-names = "calibration-data";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	};