^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) $id: http://devicetree.org/schemas/sram/sram.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) title: Generic on-chip SRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - Rob Herring <robh@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) description: |+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Simple IO memory regions to be managed by the genalloc API.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Each child of the sram node specifies a region of reserved memory. Each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) child node should use a 'reg' property to specify a specific range of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) reserved memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Following the generic-names recommended practice, node names should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) reflect the purpose of the node. Unit address (@<address>) should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) appended to the name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) $nodename:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) pattern: "^sram(@.*)?"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - mmio-sram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - atmel,sama5d2-securam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - rockchip,rk3288-pmu-sram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) A list of phandle and clock specifier pair that controls the single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) SRAM clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "#address-cells":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) const: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "#size-cells":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ranges:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Should translate from local addresses within the sram to bus addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) no-memory-wc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) The flag indicating, that SRAM memory region has not to be remapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) as write combining. WC is used by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) patternProperties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "^([a-z]*-)?sram(-section)?@[a-f0-9]+$":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) type: object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) Each child of the sram node specifies a region of reserved memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) Should contain a vendor specific string in the form
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) <vendor>,[<device>-]<usage>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) - allwinner,sun4i-a10-sram-a3-a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) - allwinner,sun4i-a10-sram-c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) - allwinner,sun4i-a10-sram-d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) - allwinner,sun9i-a80-smp-sram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) - allwinner,sun50i-a64-sram-c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) - amlogic,meson8-smp-sram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) - amlogic,meson8b-smp-sram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) - amlogic,meson-gxbb-scp-shmem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) - amlogic,meson-axg-scp-shmem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) - renesas,smp-sram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) - rockchip,rk3066-smp-sram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) - samsung,exynos4210-sysram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) - samsung,exynos4210-sysram-ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) - socionext,milbeaut-smp-sram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) IO mem address range, relative to the SRAM range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pool:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) Indicates that the particular reserved SRAM area is addressable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) and in use by another device or devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) export:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) Indicates that the reserved SRAM area may be accessed outside
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) of the kernel, e.g. by bootloader or userspace.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) protect-exec:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) Same as 'pool' above but with the additional constraint that code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) will be run from the region and that the memory is maintained as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) read-only, executable during code execution. NOTE: This region must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) be page aligned on start and end in order to properly allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) manipulation of the page attributes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) label:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) The name for the reserved partition, if omitted, the label is taken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) from the node name excluding the unit address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) const: rockchip,rk3288-pmu-sram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) else:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) - "#address-cells"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) - "#size-cells"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) - ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) sram@5c000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) compatible = "mmio-sram";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ranges = <0 0x5c000000 0x40000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) smp-sram@100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) reg = <0x100 0x50>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) device-sram@1000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) reg = <0x1000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) exported-sram@20000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) reg = <0x20000 0x20000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) export;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) // of the secondary cores. Once the core gets powered up it executes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) // code that is residing at some specific location of the SYSRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) // Therefore reserved section sub-nodes have to be added to the mmio-sram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) // declaration. These nodes are of two types depending upon secure or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) // non-secure execution environment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) sram@2020000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) compatible = "mmio-sram";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) reg = <0x02020000 0x54000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ranges = <0 0x02020000 0x54000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) smp-sram@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) compatible = "samsung,exynos4210-sysram";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) reg = <0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) smp-sram@53000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) compatible = "samsung,exynos4210-sysram-ns";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) reg = <0x53000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) // Once the core gets powered up it executes the code that is residing at a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) // specific location.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) // Therefore a reserved section sub-node has to be added to the mmio-sram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) // declaration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) sram@d9000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) compatible = "mmio-sram";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) reg = <0xd9000000 0x20000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ranges = <0 0xd9000000 0x20000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) smp-sram@1ff80 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) compatible = "amlogic,meson8b-smp-sram";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) reg = <0x1ff80 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) sram@e63c0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) compatible = "mmio-sram";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) reg = <0xe63c0000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ranges = <0 0xe63c0000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) smp-sram@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) compatible = "renesas,smp-sram";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) reg = <0 0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) sram@10080000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) compatible = "mmio-sram";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) reg = <0x10080000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) smp-sram@10080000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) compatible = "rockchip,rk3066-smp-sram";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) reg = <0x10080000 0x50>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) // Rockchip's rk3288 SoC uses the sram of pmu to store the function of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) // resume from maskrom(the 1st level loader). This is a common use of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) // the "pmu-sram" because it keeps power even in low power states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) // in the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) sram@ff720000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) reg = <0xff720000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) // primary core (cpu0). Once the core gets powered up it checks if a magic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) // value is set at a specific location. If it is then the BROM will jump
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) // to the software entry address, instead of executing a standard boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) // Also there are no "secure-only" properties. The implementation should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) // check if this SRAM is usable first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) sram@20000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) // 256 KiB secure SRAM at 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) compatible = "mmio-sram";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) reg = <0x00020000 0x40000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ranges = <0 0x00020000 0x40000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) smp-sram@1000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) // This is checked by BROM to determine if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) // cpu0 should jump to SMP entry vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) compatible = "allwinner,sun9i-a80-smp-sram";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) reg = <0x1000 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) sram@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) compatible = "mmio-sram";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) reg = <0x0 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ranges = <0 0x0 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) smp-sram@f100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) compatible = "socionext,milbeaut-smp-sram";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) reg = <0xf100 0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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