Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Microchip PIC32 Quad SPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) -----------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: Should be "microchip,pic32mzda-sqi".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg: Address and length of SQI controller register space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - interrupts: Should contain SQI interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - clocks: Should contain phandle of two clocks in sequence, one that drives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)           clock on SPI bus and other that drives SQI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - clock-names: Should be "spi_ck" and "reg_ck" in order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	sqi1: spi@1f8e2000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 		compatible = "microchip,pic32mzda-sqi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		reg = <0x1f8e2000 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		clocks = <&rootclk REF2CLK>, <&rootclk PB5CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		clock-names = "spi_ck", "reg_ck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		interrupts = <169 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	};