Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) -------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - compatible		: Should be "xlnx,zynqmp-qspi-1.0".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - reg			: Physical base address and size of GQSPI registers map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - interrupts		: Property with a value describing the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 			  number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - clock-names		: List of input clock names - "ref_clk", "pclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 			  (See clock bindings for details).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - clocks		: Clock phandles (see clock bindings for details).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - num-cs		: Number of chip selects used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	qspi: spi@ff0f0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		compatible = "xlnx,zynqmp-qspi-1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		clock-names = "ref_clk", "pclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		clocks = <&misc_clk &misc_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		interrupts = <0 15 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		interrupt-parent = <&gic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		num-cs = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 0x8000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	};