^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Cadence Xtensa XTFPGA platform SPI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This simple SPI master controller is built into xtfpga bitstreams and is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) to control daughterboard audio codec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - compatible: should be "cdns,xtfpga-spi".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) region.