Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) SPI Master controller for Netlogic XLP MIPS64 SOCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) ==================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Currently this SPI controller driver is supported for the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Netlogic XLP SoCs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	XLP832, XLP316, XLP208, XLP980, XLP532
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - compatible		: Should be "netlogic,xlp832-spi".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - #address-cells	: Number of cells required to define a chip select address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 			  on the SPI bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - #size-cells		: Should be zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - reg			: Should contain register location and length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - clocks		: Phandle of the spi clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - interrupts		: Interrupt number used by this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) SPI slave nodes must be children of the SPI master node and can contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) properties described in Documentation/devicetree/bindings/spi/spi-bus.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	spi: xlp_spi@3a100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		compatible = "netlogic,xlp832-spi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		reg = <0 0x3a100 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		clocks = <&spi_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		interrupts = <34>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		interrupt-parent = <&pic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		spi_nor@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			compatible = "spansion,s25sl12801";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 			#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 			reg = <1>;	/* Chip Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			spi-max-frequency = <40000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };