Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Xilinx SPI controller Device Tree Bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) -------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - compatible		: Should be "xlnx,xps-spi-2.00.a", "xlnx,xps-spi-2.00.b" or "xlnx,axi-quad-spi-1.00.a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - reg			: Physical base address and size of SPI registers map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - interrupts		: Property with a value describing the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 			  number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - xlnx,num-ss-bits	 : Number of chip selects used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - xlnx,num-transfer-bits : Number of bits per transfer. This will be 8 if not specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	axi_quad_spi@41e00000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 			compatible = "xlnx,xps-spi-2.00.a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 			interrupt-parent = <&intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 			interrupts = <0 31 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 			reg = <0x41e00000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 			xlnx,num-ss-bits = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 			xlnx,num-transfer-bits = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)