Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Spreadtrum ADI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ADI is the abbreviation of Anolog-Digital interface, which is used to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) framework for its hardware implementation is alike to SPI bus and its timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) is compatile to SPI timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) ADI controller has 50 channels including 2 software read/write channels and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 48 hardware channels to access analog chip. For 2 software read/write channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) users should set ADI registers to access analog chip. For hardware channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) we can configure them to allow other hardware components to use it independently,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) which means we can just link one analog chip address to one hardware channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) then users can access the mapped analog chip address by this hardware channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) triggered by hardware components instead of ADI software channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Thus we introduce one property named "sprd,hw-channels" to configure hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) channels, the first value specifies the hardware channel id which is used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) transfer data triggered by hardware automatically, and the second value specifies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) the analog chip address where user want to access by hardware components.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Since we have multi-subsystems will use unique ADI to access analog chip, when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) one system is reading/writing data by ADI software channels, that should be under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) one hardware spinlock protection to prevent other systems from reading/writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) data by ADI software channels at the same time, or two parallel routine of setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ADI registers will make ADI controller registers chaos to lead incorrect results.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Then we need one hardware spinlock to synchronize between the multiple subsystems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) The new version ADI controller supplies multiple master channels for different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) subsystem accessing, that means no need to add hardware spinlock to synchronize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) thus change the hardware spinlock support to be optional to keep backward
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) compatibility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - compatible: Should be "sprd,sc9860-adi".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - reg: Offset and length of ADI-SPI controller register space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - #address-cells: Number of cells required to define a chip select address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	on the ADI-SPI bus. Should be set to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - #size-cells: Size of cells required to define a chip select address size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	on the ADI-SPI bus. Should be set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - hwlocks: Reference to a phandle of a hwlock provider node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - hwlock-names: Reference to hwlock name strings defined in the same order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	as the hwlocks, should be "adi".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - sprd,hw-channels: This is an array of channel values up to 49 channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	The first value specifies the hardware channel id which is used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	transfer data triggered by hardware automatically, and the second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	value specifies the analog chip address where user want to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	by hardware components.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SPI slave nodes must be children of the SPI controller node and can contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) properties described in Documentation/devicetree/bindings/spi/spi-bus.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	adi_bus: spi@40030000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		compatible = "sprd,sc9860-adi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		reg = <0 0x40030000 0 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		hwlocks = <&hwlock1 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		hwlock-names = "adi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		sprd,hw-channels = <30 0x8c20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	};