Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Binding for MTK SPI Slave controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: should be one of the following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)     - mediatek,mt2712-spi-slave: for mt2712 platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - reg: Address and length of the register set for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - interrupts: Should contain spi interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - clocks: phandles to input clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   It's clock gate, and should be <&infracfg CLK_INFRA_AO_SPI1>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - clock-names: should be "spi" for the clock gate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - assigned-clock-parents: parent of mux clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   It's PLL, and should be one of the following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)    -  <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 				       It's the default one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)    -  <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)    -  <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)    -  <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - SoC Specific Portion:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) spis1: spi@10013000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	compatible = "mediatek,mt2712-spi-slave";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	reg = <0 0x10013000 0 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	clocks = <&infracfg CLK_INFRA_AO_SPI1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	clock-names = "spi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };