Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) title: SiFive SPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - Pragnesh Patel <pragnesh.patel@sifive.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   - Paul Walmsley  <paul.walmsley@sifive.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   - Palmer Dabbelt <palmer@sifive.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) allOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   - $ref: "spi-controller.yaml#"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)       - const: sifive,fu540-c000-spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)       - const: sifive,spi0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)     description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)       Should be "sifive,<chip>-spi" and "sifive,spi<version>".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)       Supported compatible strings are -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)       "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)       onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)       SPI v0 IP block with no chip integration tweaks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)       Please refer to sifive-blocks-ip-versioning.txt for details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)       SPI RTL that corresponds to the IP block version numbers can be found here -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)       https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)   reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)     minItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)       - description: SPI registers region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)       - description: Memory mapped flash region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)   interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)   clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)     description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)       Must reference the frequency given to the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)   sifive,fifo-depth:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)     description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)       Depth of hardware queues; defaults to 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)     $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)     enum: [8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)     default: 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)   sifive,max-bits-per-word:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)     description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)       Maximum bits per word; defaults to 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)     $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)     enum: [0, 1, 2, 3, 4, 5, 6, 7, 8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)     default: 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)   - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)   - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)   - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)   - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unevaluatedProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)     spi: spi@10040000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)       compatible = "sifive,fu540-c000-spi", "sifive,spi0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)       reg = <0x10040000 0x1000>, <0x20000000 0x10000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)       interrupt-parent = <&plic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)       interrupts = <51>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)       clocks = <&tlclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)       #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)       #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)       sifive,fifo-depth = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)       sifive,max-bits-per-word = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)     };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ...