Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * NXP Flex Serial Peripheral Interface (FSPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)   - compatible : Should be "nxp,lx2160a-fspi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 			    "nxp,imx8qxp-fspi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 			    "nxp,imx8mm-fspi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)   - reg :        First contains the register location and length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)                  Second contains the memory mapping address and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - reg-names :  Should contain the resource reg names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	         - fspi_base: configuration register address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)                  - fspi_mmap: memory mapped address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   - interrupts : Should contain the interrupt for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Required SPI slave node properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   - reg :        There are two buses (A and B) with two chip selects each.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)                  This encodes to which bus and CS the flash is connected:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)                  - <0>: Bus A, CS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)                  - <1>: Bus A, CS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)                  - <2>: Bus B, CS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)                  - <3>: Bus B, CS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Example showing the usage of two SPI NOR slave devices on bus A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) fspi0: spi@20c0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	compatible = "nxp,lx2160a-fspi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	reg = <0x0 0x20c0000 0x0 0x10000>, <0x0 0x20000000 0x0 0x10000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	reg-names = "fspi_base", "fspi_mmap";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	interrupts = <0 25 0x4>; /* Level high type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	clock-names = "fspi_en", "fspi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	mt35xu512aba0: flash@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	mt35xu512aba1: flash@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };