Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Binding for MTK SPI controller (MT7621 MIPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: Should be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)   - "ralink,mt7621-spi": for mt7621/mt7628/mt7688 platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - #address-cells: should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - #size-cells: should be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - reg: Address and length of the register set for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - resets: phandle to the reset controller asserting this device in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)           reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   See ../reset/reset.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - cs-gpios: see spi-bus.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - SoC Specific Portion:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) spi0: spi@b00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	compatible = "ralink,mt7621-spi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	reg = <0xb00 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	resets = <&rstctrl 18>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	reset-names = "spi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };