Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Binding for MTK SPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: should be one of the following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)     - mediatek,mt2701-spi: for mt2701 platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)     - mediatek,mt2712-spi: for mt2712 platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)     - mediatek,mt6589-spi: for mt6589 platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)     - mediatek,mt6765-spi: for mt6765 platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)     - mediatek,mt7622-spi: for mt7622 platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)     - "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)     - mediatek,mt8135-spi: for mt8135 platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)     - mediatek,mt8173-spi: for mt8173 platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)     - mediatek,mt8183-spi: for mt8183 platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)     - "mediatek,mt8192-spi", "mediatek,mt6765-spi": for mt8192 platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)     - "mediatek,mt8516-spi", "mediatek,mt2712-spi": for mt8516 platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - #address-cells: should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - #size-cells: should be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - reg: Address and length of the register set for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - interrupts: Should contain spi interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - clocks: phandles to input clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)   The first should be one of the following. It's PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)    -  <&clk26m>: specify parent clock 26MHZ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)    -  <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 				      It's the default one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)    -  <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)    -  <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)    -  <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)   The second should be <&topckgen CLK_TOP_SPI_SEL>. It's clock mux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)   The third is <&pericfg CLK_PERI_SPI0>. It's clock gate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - clock-names: shall be "parent-clk" for the parent clock, "sel-clk" for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)   muxes clock, and "spi-clk" for the clock gate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) -cs-gpios: see spi-bus.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)   controller used. This is an array, the element value should be 0~3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)   only required for MT8173.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)     0: specify GPIO69,70,71,72 for spi pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)     1: specify GPIO102,103,104,105 for spi pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)     2: specify GPIO128,129,130,131 for spi pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)     3: specify GPIO5,6,7,8 for spi pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) - SoC Specific Portion:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) spi: spi@1100a000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	compatible = "mediatek,mt8173-spi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	reg = <0 0x1100a000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		 <&topckgen CLK_TOP_SPI_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		 <&pericfg CLK_PERI_SPI0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	clock-names = "parent-clk", "sel-clk", "spi-clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	mediatek,pad-select = <1>, <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };