Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Lantiq Synchronous Serial Controller (SSC) SPI master driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)   "intel,lgm-spi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - #address-cells: see spi-bus.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - #size-cells: see spi-bus.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - reg: address and length of the spi master registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   For compatible "intel,lgm-ssc" - the common interrupt number for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   all of tx rx & err interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)        or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   For rest of the compatibles, should contain the "spi_rx", "spi_tx" and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   "spi_err" interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - clocks: spi clock phandle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - num-cs: see spi-bus.txt, set to 8 if unset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - base-cs: the number of the first chip select, set to 1 if unset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) spi: spi@e100800 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	reg = <0xE100800 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	interrupt-parent = <&icu0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	interrupts = <22 23 24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	interrupt-names = "spi_rx", "spi_tx", "spi_err";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	num-cs = <6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	base-cs = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ssc0: spi@e0800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	compatible = "intel,lgm-spi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	reg = <0xe0800000 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	interrupt-parent = <&ioapic1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	interrupts = <35 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	clocks = <&cgu0 LGM_CLK_NGI>, <&cgu0 LGM_GCLK_SSC0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	clock-names = "freq", "gate";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };