Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) ARM Freescale DSPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible : must be one of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	"fsl,vf610-dspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	"fsl,ls1021a-v1.0-dspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	"fsl,ls1012a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	"fsl,ls1028a-dspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	"fsl,ls1043a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	"fsl,ls1046a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	"fsl,ls1088a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	"fsl,ls2080a-dspi" (optionally followed by "fsl,ls2085a-dspi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	"fsl,ls2085a-dspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	"fsl,lx2160a-dspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - reg : Offset and length of the register set for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - interrupts : Should contain SPI controller interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clocks: from common clock binding: handle to dspi clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - clock-names: from common clock binding: Shall be "dspi".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - pinctrl-0: pin control group to be used for this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - pinctrl-names: must contain a "default" entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - spi-num-chipselects : the number of the chipselect signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Optional property:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - big-endian: If present the dspi device's registers are implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)   in big endian mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - bus-num : the slave chip chipselect signal number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Optional SPI slave node properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)   select and the start of clock signal, at the start of a transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)   signal and deactivating chip select, at the end of a transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) dspi0@4002c000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	compatible = "fsl,vf610-dspi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	reg = <0x4002c000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	interrupts = <0 67 0x04>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	clocks = <&clks VF610_CLK_DSPI0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	clock-names = "dspi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	spi-num-chipselects = <5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	bus-num = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	pinctrl-0 = <&pinctrl_dspi0_1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	big-endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	sflash: at26df081a@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		compatible = "atmel,at26df081a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		spi-max-frequency = <16000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		spi-cpol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		spi-cpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		linux,modalias = "m25p80";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		modal = "at26df081a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		fsl,spi-cs-sck-delay = <100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		fsl,spi-sck-cs-delay = <50>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)