^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Davinci SPI controller device bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Links on DM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - #address-cells: number of cells required to define a chip select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) address on the SPI bus. Should be set to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - #size-cells: should be zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - reg: Offset and length of SPI controller register space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - num-cs: Number of chip selects. This includes internal as well as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) GPIO chip selects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - ti,davinci-spi-intr-line: interrupt line used to connect the SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) IP to the interrupt controller within the SoC. Possible values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) are 0 and 1. Manual says one of the two possible interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) lines can be tied to the interrupt controller. Set this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) based on a specific SoC configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - interrupts: interrupt number mapped to CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - clocks: spi clk phandle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) For 66AK2G this property should be set per binding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Documentation/devicetree/bindings/clock/ti,sci-clk.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) SoC-specific Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) The following are mandatory properties for Keystone 2 66AK2G SoCs only:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - power-domains: Should contain a phandle to a PM domain provider node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) and an args specifier containing the SPI device id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) value. This property is as per the binding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) Optional:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - cs-gpios: gpio chip selects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) For example to have 3 internal CS and 2 GPIO CS, user could define
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) where first three are internal CS and last two are GPIO CS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Optional properties for slave devices:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SPI slave nodes can contain the following properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Not all SPI Peripherals from Texas Instruments support this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Please check SPI peripheral documentation for a device before using these.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - ti,spi-wdelay : delay between transmission of words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) (SPIFMTn.WDELAY, SPIDAT1.WDEL) must be specified in number of SPI module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) clock periods.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) delay = WDELAY * SPI_module_clock_period + 2 * SPI_module_clock_period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Below is timing diagram which shows functional meaning of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "ti,spi-wdelay" parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SPI_CLK | | | | | | | | | | | | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) +----------+ +-+ +-+ +-+ +-+ +---------------------------+ +-+ +-+ +-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) SPI_SOMI/SIMO+-----------------+ +-----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) +----------+ word1 +---------------------------+word2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) +-----------------+ +-----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) WDELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) <-------------------------->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) Example of a NOR flash slave device (n25q032) connected to DaVinci
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SPI controller device over the SPI bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) spi0:spi@20bf0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) compatible = "ti,dm6446-spi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) reg = <0x20BF0000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) num-cs = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ti,davinci-spi-intr-line = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) interrupts = <338>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) clocks = <&clkspi>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) flash: n25q032@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) compatible = "st,m25p32";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) spi-max-frequency = <25000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ti,spi-wdelay = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) partition@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) label = "u-boot-spl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) reg = <0x0 0x80000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) read-only;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) partition@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) label = "test";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) reg = <0x80000 0x380000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
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