Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) $id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) title: Rockchip Serial Flash Controller (SFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   - Chris Morgan <macromorgan@hotmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) allOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   - $ref: spi-controller.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)     const: rockchip,sfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)     description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)       The rockchip sfc controller is a standalone IP with version register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)       and the driver can handle all the feature difference inside the IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)       depending on the version register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)   clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)       - description: Bus Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)       - description: Module Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)   clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)       - const: clk_sfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)       - const: hclk_sfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)   power-domains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)   rockchip,sfc-no-dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)     description: Disable DMA and utilize FIFO mode only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)     type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) patternProperties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)   "^flash@[0-3]$":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)     type: object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)     properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)       reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)         minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)         maximum: 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)   - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)   - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)   - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)   - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)   - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unevaluatedProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)     #include <dt-bindings/clock/px30-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)     #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)     #include <dt-bindings/power/px30-power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)     sfc: spi@ff3a0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)         compatible = "rockchip,sfc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)         reg = <0xff3a0000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)         clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)         clock-names = "clk_sfc", "hclk_sfc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)         pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)         pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)         power-domains = <&power PX30_PD_MMC_NAND>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)         #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)         #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)         flash@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)             compatible = "jedec,spi-nor";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)             reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)             spi-max-frequency = <108000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)             spi-rx-bus-width = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)             spi-tx-bus-width = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)         };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)     };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ...