Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * ICP DAS LP-8841 SPI Controller for RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) memory register, which acts as an SPI master device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) The device uses the standard MicroWire half-duplex transfer timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Master output is set on low clock and sensed by the RTC on the rising
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) edge. Master input is set by the RTC on the trailing edge and is sensed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) by the master on low clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - #address-cells: should be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - #size-cells: should be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - compatible: should be "icpdas,lp8841-spi-rtc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - reg: should provide IO memory address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Requirements to SPI slave nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - There can be only one slave device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - The spi slave node should claim the following flags which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)   required by the spi controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)   - spi-3wire: The master itself has only 3 wire. It cannor work in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)     full duplex mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)   - spi-cs-high: DS-1302 has active high chip select line. The master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)     doesn't support active low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)   - spi-lsb-first: DS-1302 requires least significant bit first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)     transfers. The master only support this type of bit ordering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) spi@901c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	compatible = "icpdas,lp8841-spi-rtc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	reg = <0x901c 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	rtc@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		compatible = "maxim,ds1302";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		spi-max-frequency = <500000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		spi-3wire;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		spi-lsb-first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		spi-cs-high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };