Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) $id: http://devicetree.org/schemas/spi/fsl-imx-cspi.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) title: Freescale (Enhanced) Configurable Serial Peripheral Interface (CSPI/eCSPI) for i.MX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - Shawn Guo <shawnguo@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) allOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   - $ref: "/schemas/spi/spi-controller.yaml#"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)     oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)       - const: fsl,imx1-cspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)       - const: fsl,imx21-cspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)       - const: fsl,imx27-cspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)       - const: fsl,imx31-cspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)       - const: fsl,imx35-cspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)       - const: fsl,imx51-ecspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)       - const: fsl,imx53-ecspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)       - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)           - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)               - fsl,imx50-ecspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)               - fsl,imx6q-ecspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)               - fsl,imx6sx-ecspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)               - fsl,imx6sl-ecspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)               - fsl,imx6sll-ecspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)               - fsl,imx6ul-ecspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)               - fsl,imx7d-ecspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)               - fsl,imx8mq-ecspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)               - fsl,imx8mm-ecspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)               - fsl,imx8mn-ecspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)               - fsl,imx8mp-ecspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)           - const: fsl,imx51-ecspi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)   reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)   interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)   clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)       - description: SoC SPI ipg clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)       - description: SoC SPI per clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)   clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)       - const: ipg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)       - const: per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)   dmas:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)       - description: DMA controller phandle and request line for RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)       - description: DMA controller phandle and request line for TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)   dma-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)       - const: rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)       - const: tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)   fsl,spi-rdy-drctl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)     $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)     description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)       Integer, representing the value of DRCTL, the register controlling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)       the SPI_READY handling. Note that to enable the DRCTL consideration,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)       the SPI_READY mode-flag needs to be set too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)       Valid values are: 0 (disabled), 1 (edge-triggered burst) and 2 (level-triggered burst).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)     enum: [0, 1, 2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)   - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)   - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)   - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)   - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)   - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unevaluatedProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)     #include <dt-bindings/clock/imx5-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)     spi@70010000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)         #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)         #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)         compatible = "fsl,imx51-ecspi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)         reg = <0x70010000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)         interrupts = <36>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)         clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)                  <&clks IMX5_CLK_ECSPI1_PER_GATE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)         clock-names = "ipg", "per";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)     };