Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

3 Commits   0 Branches   0 Tags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) WM1811/WM8994/WM8958 audio CODEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) These devices support both I2C and SPI (configured with pin strapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) on the board).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)   - compatible : One of "wlf,wm1811", "wlf,wm8994" or "wlf,wm8958".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)   - reg : the I2C address of the device for I2C, the chip select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)           number for SPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)   - gpio-controller : Indicates this device is a GPIO controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)   - #gpio-cells : Must be 2. The first cell is the pin number and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)     second cell is used to specify optional parameters (currently unused).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)   - power supplies for the device, as covered in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)     Documentation/devicetree/bindings/regulator/regulator.txt, depending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)     on compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)     - for wlf,wm1811 and wlf,wm8958:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)       AVDD1-supply, AVDD2-supply, DBVDD1-supply, DBVDD2-supply, DBVDD3-supply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)       DCVDD-supply, CPVDD-supply, SPKVDD1-supply, SPKVDD2-supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)     - for wlf,wm8994:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)       AVDD1-supply, AVDD2-supply, DBVDD-supply, DCVDD-supply, CPVDD-supply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)       SPKVDD1-supply, SPKVDD2-supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)   - interrupts : The interrupt line the IRQ signal for the device is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)     connected to.  This is optional, if it is not connected then none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)     of the interrupt related properties should be specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)   - interrupt-controller : These devices contain interrupt controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)     and may provide interrupt services to other devices if they have an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)     interrupt line connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)   - #interrupt-cells: the number of cells to describe an IRQ, this should be 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)     The first cell is the IRQ number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)     The second cell is the flags, encoded as the trigger masks from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)     Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)   - clocks : A list of up to two phandle and clock specifier pairs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)   - clock-names : A list of clock names sorted in the same order as clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)                   Valid clock names are "MCLK1" and "MCLK2".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)   - wlf,gpio-cfg : A list of GPIO configuration register values. If absent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)     no configuration of these registers is performed. If any value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)     over 0xffff then the register will be left as default. If present 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)     values must be supplied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)   - wlf,micbias-cfg : Two MICBIAS register values for WM1811 or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)     WM8958.  If absent the register defaults will be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)   - wlf,ldo1ena : GPIO specifier for control of LDO1ENA input to device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)   - wlf,ldo2ena : GPIO specifier for control of LDO2ENA input to device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)   - wlf,lineout1-se : If present LINEOUT1 is in single ended mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)   - wlf,lineout2-se : If present LINEOUT2 is in single ended mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)   - wlf,lineout1-feedback : If present LINEOUT1 has common mode feedback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)     connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)   - wlf,lineout2-feedback : If present LINEOUT2 has common mode feedback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)     connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)   - wlf,ldoena-always-driven : If present LDOENA is always driven.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)   - wlf,spkmode-pu : If present enable the internal pull-up resistor on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)     the SPKMODE pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)   - wlf,csnaddr-pd : If present enable the internal pull-down resistor on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)     the CS/ADDR pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) Pins on the device (for linking into audio routes):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)   * IN1LN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)   * IN1LP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)   * IN2LN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)   * IN2LP:VXRN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)   * IN1RN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)   * IN1RP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)   * IN2RN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)   * IN2RP:VXRP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)   * SPKOUTLP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)   * SPKOUTLN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)   * SPKOUTRP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)   * SPKOUTRN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)   * HPOUT1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)   * HPOUT1R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)   * HPOUT2P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)   * HPOUT2N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)   * LINEOUT1P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)   * LINEOUT1N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)   * LINEOUT2P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)   * LINEOUT2N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) wm8994: codec@1a {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	compatible = "wlf,wm8994";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	reg = <0x1a>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	#gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	lineout1-se;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	AVDD1-supply = <&regulator>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	AVDD2-supply = <&regulator>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	CPVDD-supply = <&regulator>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	DBVDD-supply = <&regulator>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	DCVDD-supply = <&regulator>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	SPKVDD1-supply = <&regulator>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	SPKVDD2-supply = <&regulator>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };