Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) WM8903 audio CODEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This device supports I2C only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)   - compatible : "wlf,wm8903"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   - reg : the I2C address of the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   - gpio-controller : Indicates this device is a GPIO controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   - #gpio-cells : Should be two. The first cell is the pin number and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)     second cell is used to specify optional parameters (currently unused).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   - interrupts : The interrupt line the codec is connected to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   - micdet-cfg : Default register value for R6 (Mic Bias). If absent, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)     default is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)   - micdet-delay : The debounce delay for microphone detection in mS. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)     absent, the default is 100.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)   - gpio-cfg : A list of GPIO configuration register values. The list must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)     be 5 entries long. If absent, no configuration of these registers is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)     performed. If any entry has the value 0xffffffff, that GPIO's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)     configuration will not be modified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)   - AVDD-supply : Analog power supply regulator on the AVDD pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)   - CPVDD-supply : Charge pump supply regulator on the CPVDD pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)   - DBVDD-supply : Digital buffer supply regulator for the DBVDD pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)   - DCVDD-supply : Digital core supply regulator for the DCVDD pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Pins on the device (for linking into audio routes):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)   * IN1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)   * IN1R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)   * IN2L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)   * IN2R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)   * IN3L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)   * IN3R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)   * DMICDAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)   * HPOUTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)   * HPOUTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)   * LINEOUTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)   * LINEOUTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)   * LOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)   * LON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)   * ROP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)   * RON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)   * MICBIAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) wm8903: codec@1a {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	compatible = "wlf,wm8903";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	reg = <0x1a>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	interrupts = < 347 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	AVDD-supply = <&fooreg_a>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	CPVDD-supply = <&fooreg_b>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	DBVDD-supply = <&fooreg_c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	DCVDC-supply = <&fooreg_d>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	#gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	micdet-cfg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	micdet-delay = <100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	gpio-cfg = <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 		0x0600 /* DMIC_LR, output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 		0x0680 /* DMIC_DAT, input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 		0x0000 /* GPIO, output, low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 		0x0200 /* Interrupt, output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 		0x01a0 /* BCLK, input, active high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };