^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) # Copyright (C) 2019 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $id: http://devicetree.org/schemas/sound/tlv320adcx140.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - Dan Murphy <dmurphy@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) PDM microphones recording), high-performance audio, analog-to-digital
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) converter (ADC) with analog inputs supporting up to 2V RMS. The TLV320ADCX140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) family supports line and microphone Inputs, and offers a programmable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) microphone bias or supply voltage generation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Specifications can be found at:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) https://www.ti.com/lit/ds/symlink/tlv320adc3140.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) https://www.ti.com/lit/ds/symlink/tlv320adc5140.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) https://www.ti.com/lit/ds/symlink/tlv320adc6140.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - const: ti,tlv320adc3140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - const: ti,tlv320adc5140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - const: ti,tlv320adc6140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) I2C addresss of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) reset-gpios:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) GPIO used for hardware reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) areg-supply:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Regulator with AVDD at 3.3V. If not defined then the internal regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ti,mic-bias-source:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) Indicates the source for MIC Bias.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 0 - Mic bias is set to VREF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 1 - Mic bias is set to VREF × 1.096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 6 - Mic bias is set to AVDD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) enum: [0, 1, 6]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ti,vref-source:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) Indicates the source for MIC Bias.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 0 - Set VREF to 2.75V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 1 - Set VREF to 2.5V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 2 - Set VREF to 1.375V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) enum: [0, 1, 2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ti,pdm-edge-select:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) Defines the PDMCLK sampling edge configuration for the PDM inputs. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) array is defined as <PDMIN1 PDMIN2 PDMIN3 PDMIN4>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 0 - (default) Odd channel is latched on the negative edge and even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) channel is latched on the the positive edge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 1 - Odd channel is latched on the positive edge and even channel is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) latched on the the negative edge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PDMIN1 - PDMCLK latching edge used for channel 1 and 2 data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PDMIN2 - PDMCLK latching edge used for channel 3 and 4 data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PDMIN3 - PDMCLK latching edge used for channel 5 and 6 data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PDMIN4 - PDMCLK latching edge used for channel 7 and 8 data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) $ref: /schemas/types.yaml#/definitions/uint32-array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) minItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) maxItems: 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) maximum: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) default: [0, 0, 0, 0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ti,gpi-config:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) Defines the configuration for the general purpose input pins (GPI).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) The array is defined as <GPI1 GPI2 GPI3 GPI4>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 0 - (default) disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 1 - GPIX is configured as a general-purpose input (GPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 2 - GPIX is configured as a master clock input (MCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 3 - GPIX is configured as an ASI input for daisy-chain (SDIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 4 - GPIX is configured as a PDM data input for channel 1 and channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) (PDMDIN1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 5 - GPIX is configured as a PDM data input for channel 3 and channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) (PDMDIN2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 6 - GPIX is configured as a PDM data input for channel 5 and channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) (PDMDIN3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 7 - GPIX is configured as a PDM data input for channel 7 and channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) (PDMDIN4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) $ref: /schemas/types.yaml#/definitions/uint32-array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) minItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) maxItems: 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) maximum: 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) default: [0, 0, 0, 0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ti,asi-tx-drive:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) When set the device will set the Tx ASI output to a Hi-Z state for unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) data cycles. Default is to drive the output low on unused ASI cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) patternProperties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) '^ti,gpo-config-[1-4]$':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) $ref: /schemas/types.yaml#/definitions/uint32-array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) Defines the configuration and output driver for the general purpose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) output pins (GPO). These values are pairs, the first value is for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) configuration type and the second value is for the output drive type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) The array is defined as <GPO_CFG GPO_DRV>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) GPO output configuration can be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 0 - (default) disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 1 - GPOX is configured as a general-purpose output (GPO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 2 - GPOX is configured as a device interrupt output (IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 3 - GPOX is configured as a secondary ASI output (SDOUT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 4 - GPOX is configured as a PDM clock output (PDMCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) GPO output drive configuration for the GPO pins can be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 0d - (default) Hi-Z output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 1d - Drive active low and active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 2d - Drive active low and weak high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 3d - Drive active low and Hi-Z
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 4d - Drive weak low and active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 5d - Drive Hi-Z and active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ti,gpio-config:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) Defines the configuration and output drive for the General Purpose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) Input and Output pin (GPIO1). Its value is a pair, the first value is for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) the configuration type and the second value is for the output drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) type. The array is defined as <GPIO1_CFG GPIO1_DRV>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) configuration for the GPIO pin can be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 0 - disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 1 - GPIO1 is configured as a general-purpose output (GPO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 2 - (default) GPIO1 is configured as a device interrupt output (IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 3 - GPIO1 is configured as a secondary ASI output (SDOUT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 4 - GPIO1 is configured as a PDM clock output (PDMCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 8 - GPIO1 is configured as an input to control when MICBIAS turns on or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) off (MICBIAS_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 9 - GPIO1 is configured as a general-purpose input (GPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 10 - GPIO1 is configured as a master clock input (MCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 11 - GPIO1 is configured as an ASI input for daisy-chain (SDIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 12 - GPIO1 is configured as a PDM data input for channel 1 and channel 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) (PDMDIN1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 13 - GPIO1 is configured as a PDM data input for channel 3 and channel 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) (PDMDIN2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 14 - GPIO1 is configured as a PDM data input for channel 5 and channel 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) (PDMDIN3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 15 - GPIO1 is configured as a PDM data input for channel 7 and channel 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) (PDMDIN4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) output drive type for the GPIO pin can be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 0 - Hi-Z output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 1 - Drive active low and active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 2 - (default) Drive active low and weak high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 3 - Drive active low and Hi-Z
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 4 - Drive weak low and active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 5 - Drive Hi-Z and active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) allOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) - $ref: /schemas/types.yaml#/definitions/uint32-array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) - minItems: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) maxItems: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) maximum: 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) default: [2, 2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #include <dt-bindings/gpio/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) i2c0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) codec: codec@4c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) compatible = "ti,tlv320adc5140";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) reg = <0x4c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ti,mic-bias-source = <6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ti,pdm-edge-select = <0 1 0 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ti,gpi-config = <4 5 6 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ti,gpio-config = <10 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ti,gpo-config-1 = <0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ti,gpo-config-2 = <0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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