^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) $id: http://devicetree.org/schemas/sound/samsung-i2s.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) title: Samsung SoC I2S controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - Krzysztof Kozlowski <krzk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - Sylwester Nawrocki <s.nawrocki@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) samsung,s5pv210-i2s: for 8/16/24bit multichannel (5.1) I2S with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) secondary FIFO, s/w reset control and internal mux for root clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) samsung,exynos5420-i2s: for 8/16/24bit multichannel (5.1) I2S for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) playback, stereo channel capture, secondary FIFO using internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) or external DMA, s/w reset control, internal mux for root clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) source and 7.1 channel TDM support for playback; TDM (Time division
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) multiplexing) is to allow transfer of multiple channel audio data on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) single data line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) samsung,exynos7-i2s: with all the available features of Exynos5 I2S.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Exynos7 I2S has 7.1 channel TDM support for capture, secondary FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) with only external DMA and more number of root clock sampling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) frequencies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) samsung,exynos7-i2s1: I2S1 on previous samsung platforms supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) stereo channels. Exynos7 I2S1 upgraded to 5.1 multichannel with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) slightly modified bit offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - samsung,s3c6410-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - samsung,s5pv210-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - samsung,exynos5420-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - samsung,exynos7-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - samsung,exynos7-i2s1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) '#address-cells':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) const: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) '#size-cells':
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) dmas:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) minItems: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) maxItems: 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) dma-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) - const: tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) - const: rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) - const: tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) - const: rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) - const: tx-sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) assigned-clock-parents: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) assigned-clocks: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) minItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) maxItems: 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) - const: iis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) - items: # for I2S0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) - const: iis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) - const: i2s_opclk0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) - const: i2s_opclk1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) - items: # for I2S1 and I2S2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) - const: iis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) - const: i2s_opclk0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "iis" is the I2S bus clock and i2s_opclk0, i2s_opclk1 are sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) of the root clock. I2S0 has internal mux to select the source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) of root clock and I2S1 and I2S2 doesn't have any such mux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "#clock-cells":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) const: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) clock-output-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) deprecated: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) - items: # for I2S0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) - const: i2s_cdclk0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) - items: # for I2S1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) - const: i2s_cdclk1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) - items: # for I2S2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) - const: i2s_cdclk2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) description: Names of the CDCLK I2S output clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) samsung,idma-addr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) Internal DMA register base address of the audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) subsystem (used in secondary sound source).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pinctrl-0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) description: Should specify pin control groups used for this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pinctrl-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) const: default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) power-domains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "#sound-dai-cells":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) const: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) - dmas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) - dma-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #include <dt-bindings/clock/exynos-audss-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) i2s0: i2s@3830000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) compatible = "samsung,s5pv210-i2s";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) reg = <0x03830000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dmas = <&pdma0 10>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) <&pdma0 9>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) <&pdma0 8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dma-names = "tx", "rx", "tx-sec";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) clocks = <&clock_audss EXYNOS_I2S_BUS>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) <&clock_audss EXYNOS_I2S_BUS>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) <&clock_audss EXYNOS_SCLK_I2S>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) samsung,idma-addr = <0x03000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) pinctrl-0 = <&i2s0_bus>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #sound-dai-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };