^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) RT5660 audio CODEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This device supports I2C only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - compatible : "realtek,rt5660".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - reg : The I2C address of the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - clocks: The phandle of the master clock to the CODEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - clock-names: Should be "mclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - realtek,in1-differential
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - realtek,in3-differential
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Boolean. Indicate MIC1/3 input are differential, rather than single-ended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - realtek,poweroff-in-suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Boolean. If the codec will be powered off in suspend, the resume should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) added delay time for waiting codec power ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - realtek,dmic1-data-pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 0: dmic1 is not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 1: using GPIO2 pin as dmic1 data pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 2: using IN1P pin as dmic1 data pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Pins on the device (for linking into audio routes) for RT5660:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * DMIC L1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * DMIC R1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * IN1P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * IN1N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * IN2P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * IN3P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * IN3N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * SPO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * LOUTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * LOUTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) rt5660 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) compatible = "realtek,rt5660";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) reg = <0x1c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };