Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) RT5659/RT5658 audio CODEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This device supports I2C only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - compatible : One of "realtek,rt5659" or "realtek,rt5658".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg : The I2C address of the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - interrupts : The CODEC's interrupt output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - clocks: The phandle of the master clock to the CODEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - clock-names: Should be "mclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - realtek,in1-differential
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - realtek,in3-differential
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - realtek,in4-differential
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   Boolean. Indicate MIC1/3/4 input are differential, rather than single-ended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - realtek,dmic1-data-pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   0: dmic1 is not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)   1: using IN2N pin as dmic1 data pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)   2: using GPIO5 pin as dmic1 data pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   3: using GPIO9 pin as dmic1 data pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)   4: using GPIO11 pin as dmic1 data pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - realtek,dmic2-data-pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)   0: dmic2 is not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)   1: using IN2P pin as dmic2 data pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)   2: using GPIO6 pin as dmic2 data pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)   3: using GPIO10 pin as dmic2 data pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)   4: using GPIO12 pin as dmic2 data pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - realtek,jd-src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)   0: No JD is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)   1: using JD3 as JD source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - realtek,reset-gpios : The GPIO that controls the CODEC's RESET pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Pins on the device (for linking into audio routes) for RT5659/RT5658:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)   * DMIC L1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)   * DMIC R1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)   * DMIC L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)   * DMIC R2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)   * IN1P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)   * IN1N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)   * IN2P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)   * IN2N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)   * IN3P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)   * IN3N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)   * IN4P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)   * IN4N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)   * HPOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)   * HPOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)   * SPOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)   * SPOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)   * LOUTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)   * LOUTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)   * MONOOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)   * PDML
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)   * PDMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)   * SPDIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) rt5659 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	compatible = "realtek,rt5659";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	reg = <0x1b>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	realtek,ldo1-en-gpios =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 		<&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };