^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) RT5640/RT5639 audio CODEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This device supports I2C only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - compatible : One of "realtek,rt5640" or "realtek,rt5639".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - reg : The I2C address of the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - interrupts : The CODEC's interrupt output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - clocks: The phandle of the master clock to the CODEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - clock-names: Should be "mclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - realtek,in1-differential
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - realtek,in2-differential
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - realtek,in3-differential
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Boolean. Indicate MIC1/2/3 input are differential, rather than single-ended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - realtek,dmic1-data-pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 0: dmic1 is not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 1: using IN1P pin as dmic1 data pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 2: using GPIO3 pin as dmic1 data pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - realtek,dmic2-data-pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 0: dmic2 is not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 1: using IN1N pin as dmic2 data pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 2: using GPIO4 pin as dmic2 data pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - realtek,jack-detect-source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32. Valid values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 0: jack-detect is not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 1: Use GPIO1 for jack-detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 2: Use JD1_IN4P for jack-detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 3: Use JD2_IN4N for jack-detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 4: Use GPIO2 for jack-detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 5: Use GPIO3 for jack-detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 6: Use GPIO4 for jack-detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - realtek,jack-detect-not-inverted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) bool. Normal jack-detect switches give an inverted signal, set this bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) in the rare case you've a jack-detect switch which is not inverted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - realtek,over-current-threshold-microamp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32, micbias over-current detection threshold in µA, valid values are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 600, 1500 and 2000µA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - realtek,over-current-scale-factor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32, micbias over-current detection scale-factor, valid values are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 0: Scale current by 0.5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 1: Scale current by 0.75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 2: Scale current by 1.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 3: Scale current by 1.5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) Pins on the device (for linking into audio routes) for RT5639/RT5640:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * DMIC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * DMIC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * MICBIAS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * IN1P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * IN1N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * IN2P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * IN2N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * IN3P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * IN3N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * HPOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * HPOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * LOUTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * LOUTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * SPOLP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * SPOLN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * SPORP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * SPORN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) Additional pins on the device for RT5640:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * MONOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * MONON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) rt5640 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) compatible = "realtek,rt5640";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) reg = <0x1c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) realtek,ldo1-en-gpios =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };