^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) $id: http://devicetree.org/schemas/sound/rockchip-spdif.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) title: Rockchip SPDIF transceiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) The S/PDIF audio block is a stereo transceiver that allows the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) processor to receive and transmit digital audio via a coaxial or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) fibre cable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - const: rockchip,rk3066-spdif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - const: rockchip,rk3228-spdif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - const: rockchip,rk3328-spdif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - const: rockchip,rk3366-spdif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - const: rockchip,rk3368-spdif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - const: rockchip,rk3399-spdif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - const: rockchip,rk3568-spdif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - const: rockchip,rk3588-spdif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - rockchip,rk3188-spdif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - rockchip,rk3288-spdif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - rockchip,rk3308-spdif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - const: rockchip,rk3066-spdif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - description: clock for SPDIF bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - description: clock for SPDIF controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - const: mclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - const: hclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) dmas:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) dma-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) const: tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) power-domains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) rockchip,grf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) $ref: /schemas/types.yaml#/definitions/phandle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) The phandle of the syscon node for the GRF register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) Required property on RK3288.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "#sound-dai-cells":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) const: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) - dmas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) - dma-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) - "#sound-dai-cells"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) const: rockchip,rk3288-spdif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) then:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) - rockchip,grf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #include <dt-bindings/clock/rk3188-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) spdif: spdif@1011e000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) reg = <0x1011e000 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) clock-names = "mclk", "hclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dmas = <&dmac1_s 8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dma-names = "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #sound-dai-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };