^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) $id: http://devicetree.org/schemas/sound/rockchip-i2s.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) title: Rockchip I2S controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) The I2S bus (Inter-IC sound bus) is a serial link for digital
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) audio data transfer between devices in the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - const: rockchip,rk3066-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - rockchip,px30-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - rockchip,rk1808-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - rockchip,rk3036-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - rockchip,rk3128-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - rockchip,rk3188-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - rockchip,rk3228-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - rockchip,rk3288-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - rockchip,rk3308-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - rockchip,rk3328-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - rockchip,rk3366-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - rockchip,rk3368-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - rockchip,rk3399-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - rockchip,rv1126-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - const: rockchip,rk3066-i2s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - description: clock for I2S controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - description: clock for I2S BUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) - const: i2s_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) - const: i2s_hclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) dmas:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) minItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) maxItems: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) dma-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) - const: rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) - const: tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) - const: rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) power-domains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) reset-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) - const: reset-m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) - const: reset-h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) resets:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) maxItems: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) rockchip,capture-channels:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) default: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) Max capture channels, if not set, 2 channels default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) rockchip,playback-channels:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) default: 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) Max playback channels, if not set, 8 channels default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) rockchip,grf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) $ref: /schemas/types.yaml#/definitions/phandle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) The phandle of the syscon node for the GRF register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) Required property for controllers which support multi channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) playback/capture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "#sound-dai-cells":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) - dmas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) - dma-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) - "#sound-dai-cells"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #include <dt-bindings/clock/rk3288-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #include <dt-bindings/interrupt-controller/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) i2s@ff890000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) reg = <0xff890000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clock-names = "i2s_clk", "i2s_hclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dmas = <&pdma1 0>, <&pdma1 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dma-names = "tx", "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) rockchip,capture-channels = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) rockchip,playback-channels = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #sound-dai-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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