Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) PCM512x audio CODECs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) These devices support both I2C and SPI (configured with pin strapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) on the board).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)   - compatible : One of "ti,pcm5121", "ti,pcm5122", "ti,pcm5141" or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)                  "ti,pcm5142"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   - reg : the I2C address of the device for I2C, the chip select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)           number for SPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   - AVDD-supply, DVDD-supply, and CPVDD-supply : power supplies for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)     device, as covered in bindings/regulator/regulator.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)   - clocks : A clock specifier for the clock connected as SCLK.  If this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)     is absent the device will be configured to clock from BCLK.  If pll-in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)     and pll-out are specified in addition to a clock, the device is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)     configured to accept clock input on a specified gpio pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   - pll-in, pll-out : gpio pins used to connect the pll using <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)     through <6>.  The device will be configured for clock input on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)     given pll-in pin and PLL output on the given pll-out pin.  An
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)     external connection from the pll-out pin to the SCLK pin is assumed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	pcm5122: pcm5122@4c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		compatible = "ti,pcm5122";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		reg = <0x4c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		AVDD-supply = <&reg_3v3_analog>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		DVDD-supply = <&reg_1v8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		CPVDD-supply = <&reg_3v3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	pcm5142: pcm5142@4c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		compatible = "ti,pcm5142";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		reg = <0x4c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		AVDD-supply = <&reg_3v3_analog>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		DVDD-supply = <&reg_1v8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		CPVDD-supply = <&reg_3v3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		clocks = <&sck>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		pll-in = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		pll-out = <6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	};