Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Texas Instruments OMAP2+ McBSP module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: "ti,omap2420-mcbsp" for McBSP on OMAP2420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	      "ti,omap2430-mcbsp" for McBSP on OMAP2430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	      "ti,omap3-mcbsp" for McBSP on OMAP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	      "ti,omap4-mcbsp" for McBSP on OMAP4 and newer SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - reg: Register location and size, for OMAP4+ as an array:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)        <MPU access base address, size>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)        <L3 interconnect address, size>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - reg-names: Array of strings associated with the address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - interrupts: Interrupt numbers for the McBSP port, as an array in case the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	      McBSP IP have more interrupt lines:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	<OCP compliant irq>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	<TX irq>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	<RX irq>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - interrupt-names: Array of strings associated with the interrupt numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - ti,buffer-size: Size of the FIFO on the port (OMAP2430 and newer SoC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - ti,hwmods: Name of the hwmod associated to the McBSP port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) mcbsp2: mcbsp@49022000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	compatible = "ti,omap3-mcbsp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	reg = <0x49022000 0xff>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	      <0x49028000 0xff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	reg-names = "mpu", "sidetone";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	interrupts = <0 17 0x4>, /* OCP compliant interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		     <0 62 0x4>, /* TX interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		     <0 63 0x4>, /* RX interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		     <0 4 0x4>;  /* Sidetone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	interrupt-names = "common", "tx", "rx", "sidetone";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	interrupt-parent = <&intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	ti,buffer-size = <1280>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	ti,hwmods = "mcbsp2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };