Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Mediatek ALSA BT SCO CVSD/MSBC Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible = "mediatek,mtk-btcvsd-snd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg: register location and size of PKV and SRAM_BANK2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - interrupts: should contain BTSCO interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - mediatek,infracfg: the phandles of INFRASYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - mediatek,offset: Array contains of register offset and mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)     infra_misc_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)     infra_conn_bt_cvsd_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)     cvsd_mcu_read_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)     cvsd_mcu_write_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)     cvsd_packet_indicator_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	mtk-btcvsd-snd@18000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		compatible = "mediatek,mtk-btcvsd-snd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		reg=<0 0x18000000 0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		    <0 0x18080000 0 0x8000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		mediatek,infracfg = <&infrasys>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		mediatek,offset = <0xf00 0x800 0xfd0 0xfd4 0xfd8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	};