Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Mediatek AFE PCM controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible = "mediatek,mt8173-afe-pcm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg: register location and size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - interrupts: Should contain AFE interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - clock-names: should have these clock names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 		"infra_sys_audio_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 		"top_pdn_audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 		"top_pdn_aud_intbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 		"bck0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 		"bck1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 		"i2s0_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		"i2s1_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		"i2s2_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		"i2s3_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		"i2s3_b";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	afe: mt8173-afe-pcm@11220000  {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		compatible = "mediatek,mt8173-afe-pcm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		reg = <0 0x11220000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		clocks = <&infracfg INFRA_AUDIO>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 			<&topckgen TOP_AUDIO_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 			<&topckgen TOP_AUD_INTBUS_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 			<&topckgen TOP_APLL1_DIV0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 			<&topckgen TOP_APLL2_DIV0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 			<&topckgen TOP_I2S0_M_CK_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 			<&topckgen TOP_I2S1_M_CK_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			<&topckgen TOP_I2S2_M_CK_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 			<&topckgen TOP_I2S3_M_CK_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			<&topckgen TOP_I2S3_B_CK_SEL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		clock-names = "infra_sys_audio_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 				"top_pdn_audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 				"top_pdn_aud_intbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 				"bck0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 				"bck1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 				"i2s0_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 				"i2s1_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 				"i2s2_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 				"i2s3_m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 				"i2s3_b";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	};