Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Mediatek AFE PCM controller for mt6797
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible = "mediatek,mt6797-audio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg: register location and size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - interrupts: should contain AFE interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - power-domains: should define the power domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - clocks: Must contain an entry for each entry in clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - clock-names: should have these clock names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 		"infra_sys_audio_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 		"infra_sys_audio_26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 		"mtkaif_26m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 		"top_mux_audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		"top_mux_aud_intbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		"top_sys_pll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		"top_sys_pll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		"top_clk26m_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	afe: mt6797-afe-pcm@11220000  {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		compatible = "mediatek,mt6797-audio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		reg = <0 0x11220000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		power-domains = <&scpsys MT6797_POWER_DOMAIN_AUDIO>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		clocks = <&infrasys CLK_INFRA_AUDIO>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 			 <&infrasys CLK_INFRA_AUDIO_26M>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 			 <&infrasys CLK_INFRA_AUDIO_26M_PAD_TOP>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 			 <&topckgen CLK_TOP_MUX_AUDIO>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 			 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 			 <&topckgen CLK_TOP_SYSPLL3_D4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			 <&topckgen CLK_TOP_SYSPLL1_D4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 			 <&clk26m>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		clock-names = "infra_sys_audio_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 			      "infra_sys_audio_26m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			      "mtkaif_26m_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 			      "top_mux_audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			      "top_mux_aud_intbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			      "top_sys_pll3_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			      "top_sys_pll1_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			      "top_clk26m_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	};