^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Mediatek AFE PCM controller for mt2701
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: should be one of the followings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - "mediatek,mt2701-audio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - "mediatek,mt7622-audio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - interrupts: should contain AFE and ASYS interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - interrupt-names: should be "afe" and "asys"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - power-domains: should define the power domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - clocks: Must contain an entry for each entry in clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) See ../clocks/clock-bindings.txt for details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - clock-names: should have these clock names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "infra_sys_audio_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "top_audio_mux1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "top_audio_mux2_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) "top_audio_a1sys_hp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "top_audio_a2sys_hp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) "i2s0_src_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) "i2s1_src_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) "i2s2_src_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) "i2s3_src_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) "i2s0_src_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) "i2s1_src_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) "i2s2_src_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) "i2s3_src_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) "i2s0_mclk_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) "i2s1_mclk_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) "i2s2_mclk_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) "i2s3_mclk_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) "i2so0_hop_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) "i2so1_hop_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) "i2so2_hop_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) "i2so3_hop_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "i2si0_hop_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "i2si1_hop_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "i2si2_hop_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) "i2si3_hop_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) "asrc0_out_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) "asrc1_out_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "asrc2_out_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "asrc3_out_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "audio_afe_pd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "audio_afe_conn_pd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "audio_a1sys_pd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "audio_a2sys_pd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "audio_mrgif_pd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - assigned-clocks: list of input clocks and dividers for the audio system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) See ../clocks/clock-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - assigned-clocks-parents: parent of input clocks of assigned clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) - assigned-clock-rates: list of clock frequencies of assigned clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) Must be a subnode of MediaTek audsys device tree node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) audsys: audio-subsystem@11220000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) compatible = "mediatek,mt2701-audsys", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) afe: audio-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) compatible = "mediatek,mt2701-audio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) interrupt-names = "afe", "asys";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) clocks = <&infracfg CLK_INFRA_AUDIO>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) <&topckgen CLK_TOP_AUD_MUX1_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) <&topckgen CLK_TOP_AUD_MUX2_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) <&topckgen CLK_TOP_AUD_48K_TIMING>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) <&topckgen CLK_TOP_AUD_44K_TIMING>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) <&audsys CLK_AUD_I2SO1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) <&audsys CLK_AUD_I2SO2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) <&audsys CLK_AUD_I2SO3>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) <&audsys CLK_AUD_I2SO4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) <&audsys CLK_AUD_I2SIN1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) <&audsys CLK_AUD_I2SIN2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) <&audsys CLK_AUD_I2SIN3>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) <&audsys CLK_AUD_I2SIN4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) <&audsys CLK_AUD_ASRCO1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) <&audsys CLK_AUD_ASRCO2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) <&audsys CLK_AUD_ASRCO3>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) <&audsys CLK_AUD_ASRCO4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) <&audsys CLK_AUD_AFE>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) <&audsys CLK_AUD_AFE_CONN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) <&audsys CLK_AUD_A1SYS>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) <&audsys CLK_AUD_A2SYS>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) <&audsys CLK_AUD_AFE_MRGIF>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) clock-names = "infra_sys_audio_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "top_audio_mux1_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "top_audio_mux2_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "top_audio_a1sys_hp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "top_audio_a2sys_hp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "i2s0_src_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "i2s1_src_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "i2s2_src_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "i2s3_src_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "i2s0_src_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "i2s1_src_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "i2s2_src_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "i2s3_src_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "i2s0_mclk_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "i2s1_mclk_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "i2s2_mclk_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "i2s3_mclk_en",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "i2so0_hop_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "i2so1_hop_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "i2so2_hop_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "i2so3_hop_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "i2si0_hop_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "i2si1_hop_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "i2si2_hop_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) "i2si3_hop_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) "asrc0_out_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "asrc1_out_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "asrc2_out_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "asrc3_out_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "audio_afe_pd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "audio_afe_conn_pd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "audio_a1sys_pd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "audio_a2sys_pd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "audio_mrgif_pd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) <&topckgen CLK_TOP_AUD_MUX2_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) <&topckgen CLK_TOP_AUD_MUX1_DIV>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) <&topckgen CLK_TOP_AUD_MUX2_DIV>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) <&topckgen CLK_TOP_AUD2PLL_90M>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };