^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Freescale Synchronous Audio Interface (SAI).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The SAI is based on I2S module that used communicating with audio codecs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) which provides a synchronous audio interface that supports fullduplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) serial interfaces with frame synchronization such as I2S, AC97, TDM, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) codec/DSP interfaces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - compatible : Compatible list, contains "fsl,vf610-sai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) "fsl,imx6sx-sai", "fsl,imx6ul-sai",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "fsl,imx7ulp-sai", "fsl,imx8mq-sai" or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "fsl,imx8qm-sai".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - reg : Offset and length of the register set for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clocks : Must contain an entry for each entry in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - clock-names : Must include the "bus" for register access and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) "mclk1", "mclk2", "mclk3" for bit clock and frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) clock providing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - dmas : Generic dma devicetree binding as described in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Documentation/devicetree/bindings/dma/dma.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - dma-names : Two dmas have to be defined, "tx" and "rx".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - pinctrl-names : Must contain a "default" entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - pinctrl-NNN : One property must exist for each entry in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) pinctrl-names. See ../pinctrl/pinctrl-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) for details of the property values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - lsb-first : Configures whether the LSB or the MSB is transmitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) first for the fifo data. If this property is absent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) the MSB is transmitted first as default, or the LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) is transmitted first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) that SAI will work in the synchronous mode (sync Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) with Rx) which means both the transmitter and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) receiver will send and receive data by following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) receiver's bit clocks and frame sync clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - fsl,sai-asynchronous: This is a boolean property. If present, indicating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) that SAI will work in the asynchronous mode, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) means both transmitter and receiver will send and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) receive data by following their own bit clocks and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) frame sync clocks separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) - big-endian : Boolean property, required if all the SAI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) registers are big-endian rather than little-endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Optional properties (for mx6ul):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) - fsl,sai-mclk-direction-output: This is a boolean property. If present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) indicates that SAI will output the SAI MCLK clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) - If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) default synchronous mode (sync Rx with Tx) will be used, which means both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) transmitter and receiver will send and receive data by following clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) of transmitter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) - fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) sai2: sai@40031000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) compatible = "fsl,vf610-sai";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) reg = <0x40031000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pinctrl-0 = <&pinctrl_sai2_1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) clocks = <&clks VF610_CLK_PLATFORM_BUS>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) <&clks VF610_CLK_SAI2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) <&clks 0>, <&clks 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) clock-names = "bus", "mclk1", "mclk2", "mclk3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) dma-names = "tx", "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) big-endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) lsb-first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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