Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Dialog Semiconductor DA7212/DA7213 Audio Codec bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ======
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - compatible : Should be "dlg,da7212" or "dlg,da7213"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - reg: Specifies the I2C slave address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - clocks : phandle and clock specifier for codec MCLK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - clock-names : Clock name string for 'clocks' attribute, should be "mclk".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - dlg,micbias1-lvl : Voltage (mV) for Mic Bias 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	[<1600>, <2200>, <2500>, <3000>]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - dlg,micbias2-lvl : Voltage (mV) for Mic Bias 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	[<1600>, <2200>, <2500>, <3000>]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - dlg,dmic-data-sel : DMIC channel select based on clock edge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	["lrise_rfall", "lfall_rrise"]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - dlg,dmic-samplephase : When to sample audio from DMIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	["on_clkedge", "between_clkedge"]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - dlg,dmic-clkrate : DMIC clock frequency (Hz).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	[<1500000>, <3000000>]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  - VDDA-supply : Regulator phandle for Analogue power supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  - VDDMIC-supply : Regulator phandle for Mic Bias
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  - VDDIO-supply : Regulator phandle for I/O power supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ======
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	codec_i2c: da7213@1a {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		compatible = "dlg,da7213";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  		reg = <0x1a>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  		clocks = <&clks 201>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		clock-names = "mclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		dlg,micbias1-lvl = <2500>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		dlg,micbias2-lvl = <2500>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		dlg,dmic-data-sel = "lrise_rfall";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		dlg,dmic-samplephase = "between_clkedge";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		dlg,dmic-clkrate = <3000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	};