Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) CS42L52 audio CODEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)   - compatible : "cirrus,cs42l56"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)   - reg : the I2C address of the device for I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   - VA-supply, VCP-supply, VLDO-supply : power supplies for the device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   as covered in Documentation/devicetree/bindings/regulator/regulator.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   - cirrus,gpio-nreset : GPIO controller's phandle and the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   of the GPIO used to reset the codec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   - cirrus,chgfreq-divisor : Values used to set the Charge Pump Frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   Allowable values of 0x00 through 0x0F. These are raw values written to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)   register, not the actual frequency. The frequency is determined by the following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   Frequency = MCLK / 4 * (N+2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   N = chgfreq_val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)   MCLK = Where MCLK is the frequency of the mclk signal after the MCLKDIV2 circuit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   - cirrus,ain1a-ref-cfg, ain1b-ref-cfg : boolean, If present, AIN1A or AIN1B are configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)   as a pseudo-differential input referenced to AIN1REF/AIN3A.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   - cirrus,ain2a-ref-cfg, ain2b-ref-cfg : boolean, If present, AIN2A or AIN2B are configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)   as a pseudo-differential input referenced to AIN2REF/AIN3B.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)   - cirrus,micbias-lvl: Set the output voltage level on the MICBIAS Pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)   0 = 0.5 x VA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)   1 = 0.6 x VA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)   2 = 0.7 x VA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)   3 = 0.8 x VA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)   4 = 0.83 x VA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)   5 = 0.91 x VA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)   - cirrus,adaptive-pwr-cfg : Configures how the power to the Headphone and Lineout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)   Amplifiers adapt to the output signal levels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)   0 = Adapt to Volume Mode. Voltage level determined by the sum of the relevant volume settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)   1 = Fixed - Headphone and Line Amp supply = + or - VCP/2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)   2 = Fixed - Headphone and Line Amp supply = + or - VCP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)   3 = Adapted to Signal; Voltage level is dynamically determined by the output signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)   - cirrus,hpf-left-freq, hpf-right-freq : Sets the corner frequency (-3dB point) for the internal High-Pass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)   Filter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)   0 = 1.8Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)   1 = 119Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)   2 = 236Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)   3 = 464Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) codec: codec@4b {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	compatible = "cirrus,cs42l56";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	reg = <0x4b>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	cirrus,gpio-nreset = <&gpio 10 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	cirrus,chgfreq-divisor = <0x05>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	cirrus.ain1_ref_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	cirrus,micbias-lvl = <5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	VA-supply = <&reg_audio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };