Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) CS42L52 audio CODEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)   - compatible : "cirrus,cs42l52"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)   - reg : the I2C address of the device for I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   - cirrus,reset-gpio : GPIO controller's phandle and the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   of the GPIO used to reset the codec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   - cirrus,chgfreq-divisor : Values used to set the Charge Pump Frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   Allowable values of 0x00 through 0x0F. These are raw values written to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   register, not the actual frequency. The frequency is determined by the following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   Frequency = (64xFs)/(N+2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   N = chgfreq_val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)   Fs = Sample Rate (variable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   - cirrus,mica-differential-cfg : boolean, If present, then the MICA input is configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)   as a differential input. If not present then the MICA input is configured as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)   Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)   - cirrus,micb-differential-cfg : boolean, If present, then the MICB input is configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)   as a differential input. If not present then the MICB input is configured as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)   - cirrus,micbias-lvl: Set the output voltage level on the MICBIAS Pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)   0 = 0.5 x VA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)   1 = 0.6 x VA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)   2 = 0.7 x VA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)   3 = 0.8 x VA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)   4 = 0.83 x VA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)   5 = 0.91 x VA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) codec: codec@4a {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	compatible = "cirrus,cs42l52";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	reg = <0x4a>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	reset-gpio = <&gpio 10 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	cirrus,chgfreq-divisor = <0x05>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	cirrus.mica-differential-cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	cirrus,micbias-lvl = <5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };