Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Cirrus Logic CS4271 DT bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This driver supports both the I2C and the SPI bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  - compatible: "cirrus,cs4271"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) For required properties on SPI, please consult
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Documentation/devicetree/bindings/spi/spi-bus.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Required properties on I2C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  - reg: the i2c address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  - reset-gpio: 	a GPIO spec to define which pin is connected to the chip's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		!RESET pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  - cirrus,amuteb-eq-bmutec:	When given, the Codec's AMUTEB=BMUTEC flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 				is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  - cirrus,enable-soft-reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	The CS4271 requires its LRCLK and MCLK to be stable before its RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	line is de-asserted. That also means that clocks cannot be changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	without putting the chip back into hardware reset, which also requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	a complete re-initialization of all registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	One (undocumented) workaround is to assert and de-assert the PDN bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	in the MODE2 register. This workaround can be enabled with this DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	Note that this is not needed in case the clocks are stable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	throughout the entire runtime of the codec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  - vd-supply:	Digital power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  - vl-supply:	Logic power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  - va-supply:	Analog Power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	codec_i2c: cs4271@10 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		compatible = "cirrus,cs4271";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		reg = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		reset-gpio = <&gpio 23 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		vd-supply = <&vdd_3v3_reg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		vl-supply = <&vdd_3v3_reg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		va-supply = <&vdd_3v3_reg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	codec_spi: cs4271@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		compatible = "cirrus,cs4271";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		reg = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		reset-gpio = <&gpio 23 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		spi-max-frequency = <6000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)