^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) CS4270 audio CODEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The driver for this device currently only supports I2C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - compatible : "cirrus,cs4270"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - reg : the I2C address of the device for I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - reset-gpios : a GPIO spec for the reset pin. If specified, it will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) deasserted before communication to the codec starts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) codec: cs4270@48 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) compatible = "cirrus,cs4270";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) reg = <0x48>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };