^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) CS4265 audio CODEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This device supports I2C only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - compatible : "cirrus,cs4265"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - reg : the I2C address of the device for I2C. The I2C address depends on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) the state of the AD0 pin. If AD0 is high, the i2c address is 0x4f.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) If it is low, the i2c address is 0x4e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - reset-gpios : a GPIO spec for the reset pin. If specified, it will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) deasserted before communication to the codec starts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) codec_ad0_high: cs4265@4f { /* AD0 Pin is high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) compatible = "cirrus,cs4265";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) reg = <0x4f>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) codec_ad0_low: cs4265@4e { /* AD0 Pin is low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) compatible = "cirrus,cs4265";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) reg = <0x4e>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };