Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Atmel I2S controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible:     Should be "atmel,sama5d2-i2s".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg:            Should be the physical base address of the controller and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)                   length of memory mapped region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - interrupts:     Should contain the interrupt for the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - dmas:           Should be one per channel name listed in the dma-names property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)                   as described in atmel-dma.txt and dma.txt files.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - dma-names:      Two dmas have to be defined, "tx" and "rx".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)                   This IP also supports one shared channel for both rx and tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)                   if this mode is used, one "rx-tx" name must be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - clocks:         Must contain an entry for each entry in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)                   Please refer to clock-bindings.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - clock-names:    Should be one of each entry matching the clocks phandles list:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)                   - "pclk" (peripheral clock) Required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)                   - "gclk" (generated clock) Optional (1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)                   - "muxclk" (I2S mux clock) Optional (1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - pinctrl-0:      Should specify pin control groups used for this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - princtrl-names: Should contain only one value - "default".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) (1) : Only the peripheral clock is required. The generated clock and the I2S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)       mux clock are optional and should only be set together, when Master Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)       is required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	i2s@f8050000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		compatible = "atmel,sama5d2-i2s";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		reg = <0xf8050000 0x300>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		dmas = <&dma0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 			 AT91_XDMAC_DT_PERID(31))>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		       <&dma0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			 AT91_XDMAC_DT_PERID(32))>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		dma-names = "tx", "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		clocks = <&i2s0_clk>, <&i2s0_gclk>, <&i2s0muxck>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		clock-names = "pclk", "gclk", "muxclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		pinctrl-0 = <&pinctrl_i2s0_default>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	};