Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Atmel ClassD driver under ALSA SoC architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	Should be "atmel,sama5d2-classd".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	Should contain ClassD registers location and length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	Should contain the IRQ line for the ClassD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - dmas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	One DMA specifiers as described in atmel-dma.txt and dma.txt files.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - dma-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	Must be "tx".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	Tuple listing input clock names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	Required elements: "pclk" and "gclk".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	Please refer to clock-bindings.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - assigned-clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	Should be <&classd_gclk>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - pinctrl-names, pinctrl-0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	Please refer to pinctrl-bindings.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - atmel,model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	The user-visible name of this sound complex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	The default value is "CLASSD".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - atmel,pwm-type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	PWM modulation type, "single" or "diff".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	The default value is "single".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - atmel,non-overlap-time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	Set non-overlapping time, the unit is nanosecond(ns).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	There are four values,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	<5>, <10>, <15>, <20>, the default value is <10>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	Non-overlapping will be disabled if not specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) classd: classd@fc048000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		compatible = "atmel,sama5d2-classd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		reg = <0xfc048000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		dmas = <&dma0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 			| AT91_XDMAC_DT_PERID(47))>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		dma-names = "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		clocks = <&classd_clk>, <&classd_gclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		clock-names = "pclk", "gclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		assigned-clocks = <&classd_gclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		pinctrl-0 = <&pinctrl_classd_default>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		atmel,model = "classd @ SAMA5D2-Xplained";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		atmel,pwm-type = "diff";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		atmel,non-overlap-time = <10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };