Orange Pi5 kernel

Rockchip pvtm device tree bindings
----------------------------------

The Process-Voltage-Temperature Monitor (PVTM) is used to monitor the chip
performance variance caused by chip process, voltage and temperature.


Required properties:
- compatible: Should be one of the following.
 - "rockchip,px30-pvtm" - for PX30 SoCs.
 - "rockchip,px30-pmu-pvtm" - for PX30 SoCs.
 - "rockchip,rk1808-pvtm" - for RK1808 SoCs.
 - "rockchip,rk1808-pmu-pvtm" - for RK1808 SoCs.
 - "rockchip,rk1808-npu-pvtm" - for RK1808 SoCs.
 - "rockchip,rk3288-pvtm" - for RK3288 SoCs.
 - "rockchip,rk3308-pvtm" - for RK3308 SoCs.
 - "rockchip,rk3308-pmu-pvtm" - for RK3308 SoCs.
 - "rockchip,rk3399-pvtm" - for RK3399 SoCs.
 - "rockchip,rk3399-pmu-pvtm" - for RK3399 SoCs.
 - "rockchip,rk3568-core-pvtm" - for RK3568 SoCs.
 - "rockchip,rk3568-gpu-pvtm" - for RK3568 SoCs.
 - "rockchip,rk3568-npu-pvtm" - for RK3568 SoCs.
 - "rockchip,rk3588-bigcore0-pvtm" - for RK3588 SoCs.
 - "rockchip,rk3588-bigcore1-pvtm" - for RK3588 SoCs.
 - "rockchip,rk3588-litcore-pvtm" - for RK3588 SoCs.
 - "rockchip,rk3588-gpu-pvtm" - for RK3588 SoCs.
 - "rockchip,rk3588-npu-pvtm" - for RK3588 SoCs.
 - "rockchip,rk3588-pmu-pvtm" - for RK3588 SoCs.
 - "rockchip,rv1126-cpu-pvtm" - for RV1126 SoCs.
 - "rockchip,rv1126-npu-pvtm" - for RV1126 SoCs.
 - "rockchip,rv1126-pmu-pvtm" - for RV1126 SoCs.
- clocks: Must contain an entry for each entry in clock-names.
  See ../../clocks/clock-bindings.txt for details.
- clock-names: Should be "clk", "pclk".

Optional properties:
- resets: Must contain an entry for each entry in reset-names.
  See ../../reset/reset.txt for details.
- reset-names: Should be "rst", "rst-p".


Example:

grf: syscon@ff770000 {
	compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
	reg = <0x0 0xff770000 0x0 0x10000>;
	#address-cells = <1>;
	#size-cells = <1>;

...

	pvtm: pvtm {
		compatible = "rockchip,rk3399-pvtm";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		pvtm@0 {
			reg = <0>;
			clocks = <&cru SCLK_PVTM_CORE_L>;
			clock-names = "clk";
			resets = <&cru SRST_PVTM_CORE_L>;
			reset-names = "rst";
		};
		pvtm@1 {
			reg = <1>;
			clocks = <&cru SCLK_PVTM_CORE_B>;
			clock-names = "clk";
			resets = <&cru SRST_PVTM_CORE_B>;
			reset-names = "rst";
		};
		pvtm@2 {
			reg = <2>;
			clocks = <&cru SCLK_PVTM_DDR>;
			clock-names = "clk";
			resets = <&cru SRST_PVTM_DDR>;
			reset-names = "rst";
		};
		pvtm@3 {
			reg = <3>;
			clocks = <&cru SCLK_PVTM_GPU>;
			clock-names = "clk";
			resets = <&cru SRST_PVTM_GPU>;
			reset-names = "rst";
		};
	};
}